发明名称 METHOD OF GENERATING WIRING PROHIBIT AREA ON CELL
摘要 <p>PURPOSE:To generate a wiring prohibit area in a short time reducing the amount of held data by forming an obstacle on a cell into a rectangular area that contains a mask pattern of the same layer as the layer used for through wiring and that is through on the cell in a predetermined direction. CONSTITUTION:An obstacle is extracted from mask patterns of basic cell in advance, stored in an obstacle storage means 2 of basic cells, and coordinate values of positions of basic cells and subcells laid on a cell are stored in basic cell and subcell position coordinate storage means 3. Next, the system proceeds to an obstacle generating means 4. Obstacle generation is carried out by laying out obstacles for basic cells extracted in advance onto a cell in accordance with the sequence of the basic cells. Further, a rectangular area that contains the obstacles for the basic cells thus laid and that is through on the cell in a constant direction is generated as obstacles for the cell.</p>
申请公布号 JPH04113652(A) 申请公布日期 1992.04.15
申请号 JP19900232852 申请日期 1990.09.03
申请人 MITSUBISHI ELECTRIC CORP 发明人 TSUKAMOTO MICHIKO;NAKAO HIROOMI
分类号 G03F1/68;G03F1/70;H01L21/82 主分类号 G03F1/68
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