<p>A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described. <IMAGE></p>
申请公布号
EP0480165(A2)
申请公布日期
1992.04.15
申请号
EP19910114698
申请日期
1991.08.31
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
FERRAIOLO, FRANK DAVID;GERSBACH, JOHN EDWIN;NOVOF, ILYA IOSEPHOVICH