发明名称 MICROCOMPUTER
摘要 PURPOSE:To attain the output of the contents of a RAM, etc., by providing a means between the address/data buses and the D/A converters in order to designate and latch the digital values emerging on the address and data buses. CONSTITUTION:An internal state latch device IR 18 latches the digital values emerging on an address bus AB 9 and a data bus DB 8, and an internal state monitor selector IS 20 designates the contents to be monitored to the IR 18. These IR 18 and IS 20 are set between the AB 9/DB 8 and the D/A converters 6a/6b. Then some optional addresses are designated by a candidate RAM 5, etc., to be monitored through the IS 20 in terms of software, these designated addresses and the digital data value are outputted from the IR 18. The digital data value is converted into the analog value by the converters 6a and 6b and outputted. The contents and the types emerging on the AB 9 and DB 8 are decided in time division by a bus timing controller 11. Thus a desired subject to be monitored is specified with synchronization secured between a bus timing signal and the IS 20.
申请公布号 JPH04111145(A) 申请公布日期 1992.04.13
申请号 JP19900230942 申请日期 1990.08.31
申请人 MITSUBISHI ELECTRIC CORP 发明人 HISANAGA YUKIHISA
分类号 G06F11/28;G01R31/3167;G06F11/30;G06F13/00 主分类号 G06F11/28
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