| 摘要 |
<p>PURPOSE:To make it possible to shorten write in/erase time sharply and enlarge its scale by comprising a selection transistor so as to make available carrier conduction of both a p channel and an n channel and erasing memory by p channel operation and writing in memory by n channel operation. CONSTITUTION:This invention relates to stagger structure where a semiconductor layer 36 is staggered between a source electrode 32 and a drain electrode 34, and gate electrodes 39 and 40. The portions which include the selection electrode 40, the source electrode 32, the drain electrode 32, and a semiconductor layer 36 constitute a selection transistor Tr 11 while the portions which include the memory gate electrode 39, the source electrode 32, the drain electrode 34, and the semiconductor layer 36 constitute a memory transistor Tr 10. When phosphorous doped polysilicon (poly-Si) is used as ohmic contact layers 33 and 35, it is possible to write in or erase memory to any conduction of p channel operation and n channel operation which are characteristic of the performance of transistors.</p> |
