| 摘要 |
PURPOSE:To manufacture a semiconductor memory having a high integration degree by using the first and second masks satisfying prescribed conditions to perform patterning gate electrodes of transistors on the patterns of the piled up part of these masks. CONSTITUTION:The first masks 23 which are branched corresponding to the respective memory cells on the memory cells while being integrated in the boundary regions of the memory cells are prepared. Further, the second masks 24 having openings 24a of narrower width than the width of the masks 23 in the same boundary regions in these boundary regions are prepared. Then, patterning of the gate electrodes 14, 21, 22 of the transistors 13 is performed on the patterns of the piled-up parts of the masks 23, 34. At this time, in the boundary region of the memory cells, 1/2 of the rest, in which the width of the opening 24a of the mask 24 is reduced from the width of the mask 23 becomes the width of one each of the gate electrodes 21, 22, no patterning of the gate electrodes 14, 21, 22 is performed under a single mask. Accordingly, a wiring width a7 of the gate electrodes 21, 22 in the boundary region can be made narrow without being restricted by the limit of lithography. |
