| 摘要 |
<p>A serial-parallel converting circuit comprises a four-stage shift register circuit receiving a serial data so as to shift the received serial data through the shift register in response to each clock signal, and an output register circuit coupled in parallel to respective stages of the shift register circuit so as to fetch the content of the shift register circuit in response to a frequency-divided clock supplied from a frequency dividing circuit. The frequency dividing circuit receives the clock signal through an inverter and is composed of only two D-type flipflops and one inverter. Each of the D-type flipflops has a clock input connected to receive the clock signal in common, and the D-type flipflops are connected in series to form a shifter register. A Q output of a second flipflop is connected through the inverter to a data input of a first flipflop, so that the Q output of the last flipflop generates the frequency-divided signal. <IMAGE></p> |
