| 摘要 |
An improved symbol synchronization circuit is provided for generting a clock signal in a receiver having an input signal comprising a stream of symbols at a symbol rate of fsymbol. According to the invention, a correlator is provided that operates on a multiplicity (k) of multi-phase signals, phi 1- phi k, each signal more or less synchronized with the stream of symbols and each having a frequency fclock generally equal to a multiple of fsymbol. Based on the current synchronization of each signal phi 1- phi k with the stream of symbols, and also based on the past history of the synchronization of each signal with the stream of symbols, one member from the group of signals phi 1- phi k is periodically selected as the clock signal. This selected clock signal is then delayed to compensate for the drift between fsymbol and fclock.
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