| 摘要 |
In systems requiring multiple identical digital correlators the original m-bit counter for each correlator can be replaced by an n-bit multi-channel counter. The most significant bit of each n-bit counter is sampled every 2n-1 clock cycles and the results are stored in dual port memory. Stored input counter samples are converted into a series of binary words which are multiplexed to one of two signal outputs. The dual port memory allows current samples from the input counters to be written on port A, while previously written samples are time multiplexed and read to the output counters on port B. This design not only reduces the number of parts needed for counters but also the buffers needed for so many counters to appear on the same computer bus. In addition, the maximum delay between the sampling of any correlator is greatly reduced.
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