发明名称 CLOCK DIAL SYNCHRONOUS SYSTEM
摘要 <p>PURPOSE:To facilitate the prevention of an instantaneous second phase shift at the time of signal synchronization, a second phase shift due to instantaneous stoppage and an excessive second hand advance due to an unnecessary trigger signal respectively by providing an external judgement section for second stability to confirm the stability of a second pulse in the dial of a station clock. CONSTITUTION:An external input check counter 1 and an internal second counter 2 add pulses outputted from an interval timer 4 at intervals of 1/100 second. When a counter value reaches 100, the counters 1 and 2 are reset to zero, and the data of seconds is updated. When there is any interruption from a station clock 6, the counter 1 sets zero, and stores a counter value in registers 7a to 7c indicated by a pointer. The aforesaid setting and storing process is repeated three times, and when all counter values in the registers 7a to 7c are all equal to 99 types or above, but equal to or less than 102 types, a judgement section judges that interruption is externally taking place for the data of seconds, and outputs a synchronizing signal. The counter 2 is thereby made to reset the counter value thereof and synchronized with the counter 1.</p>
申请公布号 JPH04105092(A) 申请公布日期 1992.04.07
申请号 JP19900223017 申请日期 1990.08.24
申请人 NEC ENG LTD 发明人 MURAGUCHI HIDEAKI
分类号 G04C11/00;G04G7/00 主分类号 G04C11/00
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