| 摘要 |
The circuit includes a processor section (12) for generating channel control data, and for processing signals by accessing to common line signal data and to individual signal data. A switching section (14) switches the data of 32 channels, and an individual signal data processing section (20) controls the operation mode of a transmission interfacing section (18) to a processing mode and interfaces the output of the section (18) to the processor section (12). A 3-phase buffer (16) is switched over by the common line signals to form a transmission path through a data transmission line. A counter section (24) counts channel clocks to output common channel detection signals, and a gate (26) controls the switching of the 3-phase buffer (16). The circuit processes both common line signals and individual line signals, thereby improving the functions.
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