发明名称 TESTING SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To make it unnecessary for a simulator to execute an instruction string surely from the 1st instruction in each simulation and to shorten the testing time of a device to be tested by providing this testing system with a means for storing the status of the simulator obtained after executing the instruction string. CONSTITUTION:The testing system is provided with the device 1 to be tested, the simulator 2 in an instruction level, the status storing part 3 for storing the status of the simulator 2, an instruction generating part 4 for generating an instruction string to be executed, and an execution result comparing part 5 for comparing an execution result obtained by executing the instruction string in the device 1 to be tested with an execution result obtained by executing the instruction string by the simulator 2. In the case analyzing an error detected from the device 1 by the comparing part 5, the number of instructions to be executed by the device 1 and the simulator 2 is increased one by one from '1' based upon the same instruction string so that detecting the error to specify the position of the error. Consequently, it is unnecessary for the simulator 2 to repeat the instruction string surely from the 1st instruction in each simulation and the execution time of the simulator 2 can be shortened.
申请公布号 JPH04102931(A) 申请公布日期 1992.04.03
申请号 JP19900220245 申请日期 1990.08.22
申请人 NEC CORP 发明人 ONO TETSUYA
分类号 G06F11/22 主分类号 G06F11/22
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