发明名称 EXCEPTION PROCESSING SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To easily specify the address of a coprocessor instruction generating an exception by saving contents to be stored by a storage means in an exception processing saving area in a main storage at the time of informing exception detection from the coprocessor to the master processor. CONSTITUTION:This exception processing system is provided with a storage means 3 for storing the address of an instruction, the 1st control means 11 for storing the address including a coprocessor instruction extracted by the master processor 1 in the storage means 3 and the 2nd control means 12 for saving the contents of the means 3 to the exception processing saving area 41 of the main storage device 4 when exception detection is informed from the coprocessor 2 to the master processor 1. Even when exceptional operation is generated in the coprocessor instruction and the master processor 1 has already executed processing the coprocessor instruction to be the cause of the exception, the address including the coprocessor instruction can be known from the contents of the area 41.
申请公布号 JPH04102959(A) 申请公布日期 1992.04.03
申请号 JP19900220246 申请日期 1990.08.22
申请人 NEC CORP 发明人 SHIMIZU HIDEKAZU
分类号 G06F9/38;G06F11/00;G06F15/16 主分类号 G06F9/38
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