| 摘要 |
<p>A system comprising a cache memory (2) connected to a processor (1) and a main storage (3), wherein the processor includes means 1A for outputting a discrimination signal S designating whether the access to be made to the cache memory is a data access of continuous addresses or a data access of discontinuous addresses, and the cache memory (2) includes means 2A for handling errors in its operation on the basis of the outputted discrimination signal. During access to data of discontinuous addresses, control is so made as to suppress unnecessary accesses to the main storage. In this way, penality at the time of a failure of a cache operation is reduced and eventually, efficiency of the system can be improved as a whole by accomplishing a high speed operation</p> |
