| 摘要 |
A Single Instruction Data Transfer Apparatus A single instruction data transfer apparatus (103) which responds to a read instruction from a processor (301) is disclosed. The apparatus transfers data from a peripheral device (213, 215) to a memory device (303). Upon selection of the peripheral device (213, 215), the apparatus (103) couples the peripheral device (213, 215) to the memory device (303) via the data bus (113). Following the coupling, the apparatus (103) creates a memory (303) write signal which causes a write function to be enabled and de-asserts read signal which causes the read function to be disabled.
|
