| 摘要 |
<p>A memory controller (17) for defining memory size in an interleaved multiple bank (20A, 20D) dynamic random access memory or DRAM memory system is described. The system ensures that an associated central processing unit or CPU (10) can access a continuous memory array. The offset is selected according to the memory size. A memory controller (17) that is capable of controlling a given size DRAM selects memory below the maximum size by asserting a high or low level on the most significant address pins (Q6-Q11). By reading the input, the controller (17) can determine that memory space is not available on the higher address locations and the offset for the next bank can be determined.</p> |
