Control processor for memory bus configuration.

摘要

A control processor (11) for memory bus configuration for a parallel computer enables a plural-to-one connection of the output buses (51-58) of plural processor elements (21-24, 31-34) to memory input bus (72) and input buses (61-68) of plural processor elements to memory output bus (73), and decreases the total number of memory buses, by means of a multiplexing unit (12) which multiplexes data on the output buses of plural processor elements and transfers the multiplexed data to the memory, a demultiplexing unit (13) which demultiplexes the multiplexed data delayed by the memory and transfers the demultiplexed data to the input buses of plural processor elements, and a program control unit (14) which controls the multiplex/demultiplex formats of the multiplexing unit and the demultiplexing unit. <IMAGE>