| 摘要 |
A cell array multiplier uses unique adder interconnections to increase the multiplier output speed. More specifically, adder connections for each column of the multiplier are generated by maintaining a list of available inputs for each column. Three inputs are assigned to each full adder, wherein the inputs are chosen from the list based upon the time delay before the input is available. Once three inputs are chosen and assigned to an adder, these inputs are delected from the list and the sum of the newly assigned adder is added to the list. This process is repeated until only a sum remains on the list, which represents the output of that column. By using this method, each stage of each column is assigned the earliest available inputs possible for the column and stage in question. The present invention uses estimates of the time delays of the sum and carry for each full adder. To generate the most efficient configuration, accurate sum and carry delay estimates are necessary.
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