DATA TRANSFER CONTROL DEVICE IN MULTIPROCESSOR SYSTEM

摘要

The apparatus includes a data transmission bus requestor (2) for carrying out data transmissions and for informing it to a processor (1). A responder (2) transfers the task to a memory (4), and informs the result to the data transmission bus requestor (2). An address region encoder (12) forms an address region in accordance with the output of the processor (1), and a parity generator (13) generates parity signals for data transmissions. A slot address translator (14) generates address tags, and a tag receiver (20) receives the address tags through the system bus (3). A comparator (21) compares the address tags with the data tags. The apparatus maximizes the utilization of the system bus.