发明名称 |
SERIALIZER/DESERIALIZER WITH A TRIANGULAR MATRIX |
摘要 |
A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.
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申请公布号 |
US5101202(A) |
申请公布日期 |
1992.03.31 |
申请号 |
US19910645875 |
申请日期 |
1991.01.25 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.A. |
发明人 |
CHAISEMARTIN, PHILLIPE;ARTIERI, ALAIN |
分类号 |
G06F7/78;H03M9/00 |
主分类号 |
G06F7/78 |
代理机构 |
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