| 摘要 |
<p>PURPOSE:To prevent the malfunction of a circuit of next stage by detecting an enable signal from plural tri-state buffers (State-Buffers) of a bus (BUS) circuit so as to inhibit the output signal of an output line of the BUS circuit for an optional time. CONSTITUTION:This circuit has a function inhibiting the signal of an output line for an optional time exceeding the timing difference of enable signals of plural 3 State-Buffers of a BUS circuit. That is, an enable signal changing faster in those from two 3 State-Buffers 1, 1' is extracted and a pulse width by the transfer delay time of a delay gate 6 due to a change in the signal is extracted as a signal at the output of a differentiation circuit 4, received at the G input of a latch circuit 5 to inhibit the output of the BUS circuit. Thus, the malfunction of a D flip-flop 2 of the next stage is prevented.</p> |
