| 摘要 |
The circuit arbitrates buses of two direct memory access controllers (DMACs). The circuit includes a first flip flop for latching bus request signal of a first DMAC, a second flip flop for latching bus request signal of a second DMAC by clock invesion instruction signal, a first gate for generating a control signal to disable the second flip flop, a second gate for generating a first control signal to disable the first flip flop, a third gate for transmitting bus request signallatched by the first or the second flip flop to a bus controller, a fourth gate for transmitting a bus admission signal generated by the bus controller to the first DMAC, a fifth gate for transmitting bus admission signal to the second DMAC and a sixth gate for transmitting bus admission recognition signal to the bus controller.
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