发明名称 UNIVERSAL SCHEME OF INPUT/OUTPUT REDUNDANCY IN A PROCESS CONTROL SYSTEM
摘要 A master controller has a slave input/output processor (IOP) and a backup slave IOP, both loaded with the same data base, the backup slave IOP eavesdropping on all communications from the controller to the slave IOP to update its data base. Detection by either IOP of a fault is communicated to the other, the IOPs then failover. Finally, the controller acknowledges that the backup slave IOP is now operating as the primary source to the device. The failover occurs without any loss of communications within the control system and is transparent to the control system. <IMAGE>
申请公布号 CA2051786(A1) 申请公布日期 1992.03.27
申请号 CA19912051786 申请日期 1991.09.18
申请人 HONEYWELL INC. 发明人 MCLAUGHLIN, PAUL F.;BRISTOW, ROBERT W.
分类号 G06F11/20;G06F13/00;G06F15/16 主分类号 G06F11/20
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