| 摘要 |
PURPOSE:To reduce the test time and to improve the convenience of use by using a clock from a variable clock generating section for an input clock to a counter and setting a clock frequency optionally with an external control signal and setting freely a zone confirming time and a zone unconfirming time based on the count operation of the counter. CONSTITUTION:When a digital phase locked loop(DPLL) 1 is in operation at a lock region, an up-down(U/D) counter 6 increments an output pulse of a flip- flop(F/F) 14 and outputs a zone confirming signal when the count reaches a prescribed value, and on the other hand, when the DPLL 1 is in operation at the unlock region, the U/D counter 6 decrements the output pulse of the F/F 14 and outputs a zone unconfirming signal when the count is zero. In this case, the repetitive frequency in the output pulse of the F/F 14 is set to an optional pulse of the F/F 14 under the control of a central processing unit (CPU) 16, then the zone confirming time and the zone unconfirming time are freely set in the normal operation. Thus, the test time is remarkably reduced and the convenience of use is improved. |
