| 摘要 |
<p>PURPOSE:To enable a packet switchboard to respond to a request for the transmission or reception of data slower than the maximum processing speed only by providing a clock output permitting section which only permits the output of clocks slower than the maximum processing speed of the packet switchboard to a multiplex section. CONSTITUTION:When various kinds of transmission data 205 are transmitted to an MUX 203 and a certain channel of the data 205 has no voice or data, the MUX 203 sends a signal 220 indicating the status to a clock generation circuit 221 for transmitting packet data so as to generate a corresponding transmission clock 222. Then an AND circuit 223 takes the AND of the clock 22 and an output permit signal 211 and packet transmission data 225 are sent to the MUX 203 by supplying the output of the circuit 223 to a packet switchboard 70 as a packet transmission clock 224. The MUX 203 multiplexes the various kinds of transmission data 205 with the packet transmission data 205 and transmits the multiplexed data to a high-speed digital line 80 through an interface 202, data bus 102, and interface 103.</p> |
