| 摘要 |
<p>A logic circuit (30) for receiving both CMOS- and CML-level input voltages in one embodiment performs a logical OR function. A reference bipolar transistor (37) is coupled to a first power supply voltage terminal through a first resistor (32). A second bipolar transistor (36) for receiving a CML-level input signal is coupled to the first power supply voltage terminal through a second resistor (31). Emitters of the bipolar transistors (36, 37) are connected together. A MOS transistor (34) for receiving a CMOS-level input signal has a drain connected to a collector of the second bipolar transistor (36), and a voltage dropping portion (39) separates the source of the MOS transistor (34) from the emitters of the reference transistor (37) and the bipolar (36) transistor. The input voltages control a constant current conducted from a current source (43) connected to the source of the MOS transistor (34). <IMAGE></p> |
