| 摘要 |
PURPOSE:To unnecessitate the coincidence to be previously secured between the synchronizing output timing of a bit synchronizing circuit and the central time position of the bith length of the input data by using electrically a delay time control means to the data input and forming an analog phase synchronizing system where the system clock is used as a reference clock and the clock included in the data input is used as an input. CONSTITUTION:A clock extracting means 2 is provided to extract a synchronizing clock out of the input data together with a clock phase detection means 3 which detects a phase error between the clock extracted by the means 2 and a prescribed system clock, the delay time control means 4 and 5 which produce and output the delay time control signals in response to the level of the phase error detected by the means 3, and the voltage control delay means 1 which inputs the delay time control signal and controls the delay time to the input data. Thus it is unneccessitated to previously secure the coincidence between the central time position of the bit length of the input data and the synchronizing output timing of a bit synchronizing circuit as an initial state for the normal operation of this circuit. |
