Programmable neural logic device.

摘要

A programmable logic cell, compatible with LSSD (Level Sensitive Scan Design) technique, is described whose internal logic can be initially loaded from an EPROM or external processor. The output (234) or contents of one cell can be connected to another cell to alter the logic operation of the second cell even whilst this second cell is in operation. The cells can be connected together to form a neural network. <IMAGE> <IMAGE>