| 摘要 |
PURPOSE:To allow a variable delay circuit to change delay time while the circuit secures a sufficient logical amplitude as a variable delay circuit by providing a buffer circuit which functions as a logical gate and exclusive OR circuit which controls the delay time. CONSTITUTION:When a delay time control signal inputted to an exclusive OR circuit 2 is low in level, the output of the circuit 2 becomes the same as that of a buffer circuit l and the voltage across both ends of capacitor 3 always fluctuates in the same phase, with input signals to the circuit l being outputted as they are. On the other hand, when the delay time control signal inputted to the circuit 2 is high in level, the output of the circuit 2 becomes opposite in phase to input signals. Therefore, the voltage across both ends of the capacitor 3 always fluctuates in the opposite phase and acts on the output of the buffer circuit 1 as a capacitance. In other words, the output signal of the circuit l is outputted after it is delayed in accordance with the charging time of the capacitor 3. |
