| 摘要 |
<p>The address generator (GA) for the data storage (RAM) of a processor receives a control word (MC) from a program controller (CP), this program controller itself receiving instructions (I) originating from a program memory (ROM) addressed by an instruction counter (CI) and producing a program signal (P) destined for an arithmetic and logic unit (ALU), the instruction counter being incremented by a clock signal (Ck) and initialised by the program controller, and is characterised in that, as the control word (MC) comprises an item of installation information (IE) and an item of selection information (IS), it comprises means for producing a data address (AD) composed of a first part comprising the bits of the item of installation information (IE) and of a second part formed by a selected assembly of bits of the current instruction address (AI) identified by the item of selection information (IS). <IMAGE></p> |
