发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To shorten the phase pull-in time and to increase the frequency pull-in range by controlling the 1st and 2nd switch parts so as to output an inverted signal after detecting a 2nd phase difference based on the beat waveforms of the 1st and 2nd detection parts. CONSTITUTION:An output signal 111 of a frequency divider 10 controlled by a switch 15 is inputted to a triangular wave type phase comparator 1 to undergo the detection of the phase difference to an input signal 101. Then a beat waveform 104 is outputted by a loop filter 3. In the same way, a signal shifted by pi/2 from a signal 110 controlled by a switch 16, i.e., the signal 111 is inputted to a triangular wave type phase comparator 2 to undergo the detection of the phase difference to the signal 101. Then beat waveform 105 is outputted by a loop filter 4. Both waveforms 104 and 105 are inputted to the comparators 6 and 5 respectively. Thus it is possible to omit an undesired period, to shorten the time needed forsynchronization, and to increase a pull-in range.
申请公布号 JPH0492512(A) 申请公布日期 1992.03.25
申请号 JP19900209854 申请日期 1990.08.08
申请人 NEC CORP;NEC MIYAGI LTD 发明人 ITO YUICHI;SUZUKI HIROTAKA
分类号 H03L7/087;H03L7/10 主分类号 H03L7/087
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