| 摘要 |
<p>The invention relates to an asynchronous multiplexer with N inputs and one output, N being a power of 2. The proposed multiplexer comprises in particular a synchronisation and header-insertion loop (SIE) composed of N synchronisation and insertion blocks (SI1-SIN), to the inputs of which are respectively connected N incoming lines (L1-LN), a switching network (RCX) with N inputs (R1-RN) and N outputs (X1-XN), whose inputs (R1-RN) are respectively connected to the outputs of the synchronisation and insertion blocks (SI1-SIN), and a logic queue (FAL) consisting of N physical queues (FA1-FAN) connected into a loop, and read successively in circular sequential order, whose inputs are respectively connected to the outputs (X1-XN) of the switching network (RCX) and whose outputs are connected to the output (S0) of the multiplexer. The invention is applicable in asynchronous mode data transmission systems. <IMAGE></p> |
