OUTPUT BUFFER CIRCUITRY OF INTEGRATED CIRCUIT

摘要

The circuit includes NAND gates (ND1)(ND2) for logic- combining control signals. An inverting gate (G1) inverts the output of the NAND gate (ND1), and another inverting gate (G2) inverts the output of the NAND gate (ND2). Transistors (Q1)(Q2) are switched over in accordance with the output signals of the inverting gates (G1)(G2), and a logic-combining section (10) logic-combines the output signals of field effect transistors (Q3)(Q4), while an output section (20) charges or discharges capacitors in accordance with the output signals of the field effect transistors (Q3)(Q4). The buffer circuit of the present invention reduces the peak current by 50% to decrease the noise markedly.