| 摘要 |
<p>PURPOSE: To prevent invalid multiplex selection phenomena(IMS phenomena) at the time of a block writing mode by controlling the pulse width of a first data latch pulse with the existance of a block writing signal and generating a second data latch pulse. CONSTITUTION: The first data latch pulse having a prescribed pulse width is generated with a data latch pulse generating circuit 20 at the time of the operation of a dual port memory element. And the pulse width of the first data latch pulse is controlled with the existance of the block writing signalϕBW, and the second data latch pulse is generated with a latch circuit 30. A data input DIN or column selection signal CSLi is generated with an input buffer part 10 by using the second data latch pulse and receiving data input signal WIi. By this way, the IMS phenomena are prevented at the time of the block writing mode.</p> |
