发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To simplify the external timing by actuating one of three timing circuits according to a case where recall signal is held, a case where a store signal is held, and a case where both recall and store signals are not held respectively. CONSTITUTION:When four input signals are received and set at each prescribed level, a recall signal showing that a recall operation should be carried out and a store signal showing that a store operation should be carried out are produced and held. Then the operation of only one of three circuits, i.e., a recall timing circuit 5, a store timing circuit 6, and a read timing circuit 4 is granted in accordance with a case where the recall signal is held, a case where the store signal is held, and a case where both recall and store signals are not held respectively. Thus the operations of other two circuits are inhibited. As a result, the external input timing is simplified.
申请公布号 JPH0487099(A) 申请公布日期 1992.03.19
申请号 JP19900202958 申请日期 1990.07.30
申请人 SHARP CORP 发明人 FUKUMOTO KATSUMI
分类号 G11C14/00;G11C16/04;H01L27/10;H01L27/105 主分类号 G11C14/00
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