发明名称 A semiconductor memory with automatic test mode exit on chip enable.
摘要 <p>An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit (29) for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function. &lt;IMAGE&gt;</p>
申请公布号 EP0475589(A1) 申请公布日期 1992.03.18
申请号 EP19910307420 申请日期 1991.08.12
申请人 SGS-THOMSON MICROELECTRONICS, INC. 发明人 STEELE, RANDY CHARLES
分类号 G11C11/413;G11C11/401;G11C29/14;G11C29/46 主分类号 G11C11/413
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