| 摘要 |
PURPOSE:To increase load resistance by interposing a semi-insulating high- resistivity polycrystalline semiconductor layer not doped with impurities between a polycrystalline semiconductor layer composing high-resistance load resistors and a semiconductor layer or region connected thereto. CONSTITUTION:A contact window 16H is made by pattern etching in a part of a layer insulating layer 16 corresponding to points P1 and P2 on a wiring layer on or extended from a gate electrode 14. A semi-insulating high-resistivity polycrystalline semiconductor layer 3 not actively doped with impurities is formed on the whole surface through the contact window 16H by the CVD method and coated with a flattening material 17. The semiconductor layer 3 on the other section than the contact window 16H is removed by etching by vertical anisotropic RIE from the surface. A polycrystalline silicon layer 1 in contact with the semiconductor layer 3 in the contact window 16H is formed and etched into the desired pattern to make load resistors R1 and R2. Thereby load resistance increases substantially. |
