DRAM using word line drive circuit system.

摘要

Memory cells (MCA) include at least one memory cell (10) having an n-channel MOS transistor (17) and an n-channel MOS capacitor (16). A word line (WL) is connected to the memory cells (MCA). A word line drive circuit (11) for driving the word line (WL) includes a p-channel MOS transistor (20) for transferring a potential to the word line (WL). The word line drive circuit (11) is controlled by an output from a word line potential control circuit (15). The word line potential control circuit (15) applies a power source potential (Vcc) to the word line (WL) through the current path of the p-channel MOS transistor (20) in the word line drive circuit (11) when the memory cells (MCA) are not selected, and the word line potential control circuit (15) applies a potential higher than a potential obtained by adding a threshold voltage (VTH2) of the n-channel MOS transistor (17) to the power source potential (Vcc) to the word line (WL) through the current path of the p-channel MOS transistor (20) in the word line drive circuit (11) when the memory cells (MCA) are selected. <IMAGE>