| 摘要 |
PURPOSE:To control a direct memory access cycle time, by providing a weight number register and a weight counter. CONSTITUTION:When a DMA controller 1 receives a DMA request signal from each input/output adapter 9, a channel controller 3 of the input/output adapter 9 which is peritted to occupy a common bus 5 is determined by a priority level determining circuit 16. At this time, a DMA channel selecting signal is outputted from a bus controller 17. An initial value set instruction from a weight number resister 2 of the selected channel controller 3 to a weight counter 4 is executed, and the weight counter 4 is set. |
