| 摘要 |
<p>PURPOSE:To simply form a frame pattern detecting circuit even when clock frequency is high and a frame synchronizing pattern is long by executing the serial/parallel conversion of a receiving code string at the rate of 1:n and then detecting the frame synchronizing pattern. CONSTITUTION:At the time of executing serial/parallel conversion at the rate of l:2 e.g. pattern detecting operation is executed by both of coincidence detection circuits 5, 6 during the period of synchronizing restoration operation, and after detecting a frame synchronizing pattern by either one of the circuits 5, 6, pattern detection is executed only by the pattern coincidence detection circuit detecting the pattern. A channel exchanging circuit 14 exchanges data strings based upon information indicating whether either one of the circuits 5, 6 detects the coincidence pattern or not and data strings are outputted from data output terminals 15, 16 always in the same order independently of the initial state of a frequency dividing counter in a serial/parallel conversion circuit 3. Thereby, even when a circuit operation speed is reduced to 1/2, equivalent frame synchronizing operation can be executed. Even if the clock frequency is high and the frame synchronizing pattern is long, the frame pattern detection circuit can simply be obtained.</p> |
