发明名称 TIMING EXTRACTION CIRCUIT
摘要 PURPOSE:To extract a reception clock to fetch a reception data stably from the reception data by suppressing out of synchronism due to noise superimposed on the reception data with a flip-flop and a shift register. CONSTITUTION:A shift register 170 outputs a state signal 175 in response to the state of a reception data 100 and a change point of the reception data 100 is detected while avoiding noise by using a decoder 190 to decode the state signal 175. Moreover, the reception data 100 and a reception clock 110 are synchronized by resetting a counter 150 counting a source clock 120 and outputting the reception clock 110 or presetting a prescribed value to the counter 150 at the detection of a change point. Thus, the stable reception clock is extracted from the reception data without being affected due to noise such as spike at all times.
申请公布号 JPH0484526(A) 申请公布日期 1992.03.17
申请号 JP19900199549 申请日期 1990.07.27
申请人 NEC CORP 发明人 SASAKI YASUSHI
分类号 H03K5/1252;H03K5/01;H04L7/027 主分类号 H03K5/1252
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