发明名称 SIMULATION METHOD
摘要 PURPOSE:To enable simulation at a desired logical description level without directly designating a corresponding file by automatically selecting a logical description for each individual function block based on the designation of the logical description level. CONSTITUTION:An entire LSI model is simulated at a precise gate description level to an individual function block BL4, which is not logically certified yet, and at a rough operation description level to remaining certified individual function blocks BL1-3. At such a time, description files 1A, 2B, 3A and 4C are selected by totally designating the operation description level or individually designating the gate description to the function block BL4 and totally designating the gate description levels to the remaining blocks. Since simulation is executed while mixing the plural logical description level selected in this way, the BL4 is precisely certified at the gate level.
申请公布号 JPH0480876(A) 申请公布日期 1992.03.13
申请号 JP19900194651 申请日期 1990.07.23
申请人 HITACHI LTD 发明人 ONO YASUNOBU
分类号 G06F17/50;G06Q30/06;G06Q50/00 主分类号 G06F17/50
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