LAYOUT DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT,申请号JP19900194530-传众专利搜索

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发明名称	LAYOUT DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要
申请公布号	JPH0480878(A)	申请公布日期	1992.03.13
申请号	JP19900194530	申请日期	1990.07.23
申请人	NEC CORP	发明人	ETANI ATSUSHI
分类号	H01L21/82;G06F17/50	主分类号	H01L21/82
代理机构		代理人
主权项
地址

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