| 摘要 |
<p>PURPOSE:To transfer independent synchronous data without error by sending data with (n) sub-frames unit switching the sub-frames to network clocks, sending dummy bits regarding shortage bits, receiving the data by the network clocks at the reception side, and taking frame synchronization discarding the dummy bits and restoring the sub--frames. CONSTITUTION:By supplying network clock timing from a line interface section 6, a transmitting-side network clock control section 5 reads out data from each frame by means of network clocks by the number of effective data bits in each frame against a sending data clock switching section 4. The data are outputted to the interface section 6 after switching it to the network clocks and sending to a high-speed line. At the time of reception, a frame synchronization processing section 7 detects frame synchronization and informs a reception side network clock controlling section 8 of frame effective area information. At the section 8, effective reception data are successively buffered in a reception data clock switching section 9 in a frame-controlled form based on the network clocks and frame effective area information.</p> |
