发明名称 Decentralised access monitoring in multi-microcomputer system - monitoring time between access and quit signal and generating forced quit signal if verification time is exceeded
摘要 A method of decentralised monitoring of access to the commonly used components of a multimicrocomputer system involves providing the same max. verification time for the components. The verification period is monitored in each microprocessor from the quit signal (LRDY or GRDY) for each first access and is removed after expiry of the verification time by simultaneous activation of the interrupt input (NMI). In each microcomputer the wait time between the access request (ALE) and quit signal is monitored and a forced quit signal (FRDY or GRDY) is generated and the interrupt input activated if the time exceeds a max. verification time. USE/ADVANTAGE - Enables location and origin of access problems to be distinguished and diagnosed as verification and hardware faults.
申请公布号 DE4028317(A1) 申请公布日期 1992.03.12
申请号 DE19904028317 申请日期 1990.09.06
申请人 SIEMENS AG, 8000 MUENCHEN, DE 发明人 WIEGAND, HERMANN-JOSEF, DIPL.-ING., 8523 BAIERSDORF, DE
分类号 G06F13/372 主分类号 G06F13/372
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