发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To reduce the board mount area and to simplify the manufacture process by providing plural frequency divider circuits, plural nonvolatile memories, a control circuit and a step adjustment circuit to an oscillation circuit with rough accuracy provided in an integrated circuit. CONSTITUTION:The clock generating circuit is provided with a 1st frequency divider circuit 2 frequency-dividing an output of an oscillation circuit 1 with rough accuracy, a 2nd frequency divider circuit 4 frequency-dividing a clock further sent from an output terminal 3, a control circuit 5 controlling the frequency division ratio of the 1st frequency divider circuit 2 and a 1st nonvolatile memory 8 storing a frequency division ratio control data of the control circuit 5. Moreover, a 2nd nonvolatile memory 9 storing a temperature compensation data, a temperature measurement circuit 10, a step adjustment circuit 6 outputting a step adjustment data to the control circuit 5 based on the temperature compensation data of the 2nd nonvolatile memory 9 and the output of the 2nd frequency divider circuit 4, and a constant voltage generating circuit 7 supplying a prescribed voltage to the oscillation circuit 1 are provided. Thus, the board mount area is reduced without use of a vibrator such as crystal resonator and the manufacture process is simplified.</p>
申请公布号 JPH0479512(A) 申请公布日期 1992.03.12
申请号 JP19900191740 申请日期 1990.07.19
申请人 NEC CORP 发明人 AKASHI YOICHI
分类号 G06F1/04;H03K3/02 主分类号 G06F1/04
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