CIRCUIT CONFIGURATION FOR POTENTIAL TRIGGERING OF A FIELD EFFECT TRANSISTOR

摘要

A circuit configuration for potential-free triggering of an FET includes a source voltage terminal connected to the gate terminal of a depletion FET, and an optoelectronic coupler having a receiver circuit connected between the source terminal of the depletion FET and the source voltage terminal. A plurality of the circuit configuration may also be connected in series.