| 摘要 |
PURPOSE:To attain high speed read without address input by forming a block for a comparison data at each channel and transferring the data from a RAm to a SAM altogether. CONSTITUTION:A large capacity of comparison dats area is ensured by storing a comparison data in a 2-port DRAM 25. Further, a circuit 20 synchronizing the timing for block transfer of the data from the RAM 32 to the SAM 33 with the timing of serial/parallel conversion of a sampling data 1 on a serial communication line is added to transfer the data of all channels for one data comparison from the RAM to the SAM altogether. Thus, the data of all channels for one data comparison are transferred altogether from the RAM to the SAM. Thus, the access of a 2-port RAM at the data comparison is limited to a serial read cycle by a shift pulse of the SAM to attain the read of the comparison data without any address input is attained at a high speed.
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