DIGITAL PHASE LOCK LOOP

摘要

A digital phase lock loop utilizing a programmable delay line to phase shift the output of a crystal generated reference clock signal and lock it to digitized data transitions recorded on a suitable medium is provided. The output of the delay line is compared to the digitized data transitions in a phase detector to determine if the delay line output leads or lags the data transitions. The delay line is then reprogrammed to reduce the phase difference between the data transition and the delay output to a minimum value.