| 摘要 |
<p>PURPOSE:To reduce the electric field stress applied to a memory cell, and to extend the service life of the memory cell by setting all word lines at the time of stand-by, and word lines of a memory cell matrix which does not contain a selective memory cell at the time of active to an [L] level. CONSTITUTION:An X decoder circuit 104 contains a means for setting all word lines Wjk to a low level by a control signals Sj from a partial circuit 302 at the time of stand-by, and setting all word lines in a memory cell matrix which does not contain a selective memory cell to a low level at the time of active. Also, the X decoder circuit 104 contains a first NAND circuit 11 to which plural address input signals a3, a4 are inputted, a second and a third NAND circuits 12, 13, a P channel MOS transistor 14, and an N channel MOS transistor 15 whose source is connected to a ground potential GND, respectively. In such a way, an electric field stress applied unnecessarily to a memory cell is reduced, and the reliability can be improved.</p> |
