| 摘要 |
PURPOSE:To make it possible to perform a specification of operating speed control stages and a verification of the operating speed of an arbitrary pipeline stage on the basis of an arbitrary instruction by a method wherein all internal latches are divided into (n) pieces of groups of latches, either of a normal operation clock and an operating speed verification clock is selected by (n) pieces of selective means and the clocks are respectively inputted in the (n) pieces of the groups of latches. CONSTITUTION:When the verification of the operating speed of a group 12 of instruction read stage ph1 latches is performed, an operating speed verification tph 1 clock 23, which is outputted from an operating speed verification clock generating circuit 2, is selected by a selective means 4 for the group 12 of instruction read stage ph1 latches on the basis of a selection signal 26, which is outputted from an operating speed verification detecting circuit 3, and is inputted in the group 12 as an internal operation ph1 clock 34. Other selective means 5 to 11 select a normal operation ph1 clock 21 or a normal operation ph2 clock 22, which is outputted from a normal operation clock generating circuit 1, on the basis of selection signals 27 to 33 and is outputted to groups of latches other than the group 12 as internal operation ph1 clocks 35 to 41. Moreover, addresses, which are outputted to external pins, or data are compared with the respective expected values of the addresses or the data and whether the operation of a microprocessor is a normal operation or an erroneous operation or not is judged. |
